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CAT25C128/256
128K/256K-Bit SPI Serial CMOS E2PROM FEATURES
s 5 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive s 100,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s 64-Byte Page Write Buffer s Block Write Protection
Temperature Ranges
- Protect 1/4, 1/2 or all of E2PROM Array
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial CMOS E2PROM internally organized as 16Kx8/32Kx8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25C128/256 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C128/ 256 is designed with software and hardware write protection features including Block Lock protection. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
SOIC Package (S, K) TSSOP Package (U14)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
BLOCK DIAGRAM
DIP Package (P)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
SENSE AMPS SHIFT REGISTERS
SOIC Package (S16)
CS SO NC NC NC NC WP VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI
CS SO NC NC NC WP VSS
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC HOLD NC NC NC SCK SI
WORD ADDRESS BUFFERS
COLUMN DECODERS
TSSOP Package (U20)
NC CS SO SO NC NC WP VSS NC NC
PIN FUNCTIONS Pin Name
SO SCK WP VCC VSS CS SI HOLD NC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC VCC HOLD HOLD NC NC SCK SI NC NC
SO SI CS WP HOLD SCK
I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC
CONTROL LOGIC
XDEC
E2PROM ARRAY
Function
Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect
STATUS REGISTER
DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL
25C128 F02
Note: CAT25C256 not available in 8-Lead S or U packages.
Doc. No. 25088-00 1/01
(c) 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS(1) .................. -2.0V to +VCC +2.0V VCC with Respect to VSS ................................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 100,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VIL(3) VIH(3) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC - 0.8 0.2 -1 VCC x 0.7 Min. Typ. Max. 10 2 0 2 3 VCC x 0.3 VCC + 0.5 0.4 Units mA mA A A A V V V V V V 4.5VVCC<5.5V IOL = 3.0mA IOH = -1.6mA 1.8VVCC<2.7V IOL = 150A IOH = -100A VOUT = 0V to VCC, CS = 0V Test Conditions VCC = 5V @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK = 5MHz CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
Doc. No. 25088-00 1/01
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CAT25C128/256
Figure 1. Sychronous Data Timing
VIH tCS
CS
VIL tCSS VIH tCSH
SCK
VIL tSU VIH
tWH tH
tWL
SI
VIL
VALID IN
tRI
tFI
tV VOH
tHO
tDIS HI-Z
SO
VOL
HI-Z
Note: Dashed Line= mode (1, 1) -- -- -- --
A.C. CHARACTERISTICS (CAT25C128)
Limits Vcc= 1.8V-6.0V SYMBOL tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC tV tHO tDIS tHZ tCS tCSS tCSH tWPS tWPH PARAMETER Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time WP Hold Time 1000 1000 1000 50 50 0 250 150 250 250 250 50 50 250 250 10 250 0 250 150 100 100 100 50 50 Min. 100 100 250 250 DC 1 50 2 2 250 250 10 250 0 100 50 Max. VCC = 2.5V-6.0V Min. 70 70 150 150 DC 3 50 2 2 40 40 5 80 Max. VCC = 4.5V-5.5V Min. 35 35 80 80 DC 5 50 2 2 Max. UNITS ns ns ns ns MHz ns s s ns ns ms ns ns ns ns ns ns ns ns ns Test Conditions
CL = 50pF
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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Doc. No. 25088-00 1/01
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256) Limits Vcc= 1.8V-6.0V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC tV tHO tDIS tHZ tCS tCSS tCSH tWPS tWPH NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
VCC= 2.5V-6.0V 100 100 250 250
VCC= 2.7V-6.0V 70 70 200 200
VCC = 4.5V-5.5V 35 35 80 80 ns ns ns ns 5 50 2 2 40 40 MHz ns s s ns ns 5 80 0 ms ns ns 100 50 100 100 100 50 50 ns ns ns ns ns ns ns
Test
Min. Max. Min. 500 500 2500 2500 DC 0.2 100 2 2 250 250 10 250 0 250 150 100 100 100 50 50 100 100 100 50 50 0 100 100
Max. Min. Max. Min. Max. UNITSConditions
Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time WP Hold Time
DC
2.0 50 2 2
DC
2.5 50 2 2
DC
100 100 10 200 0 200 100 100 100 100 50 50 200 100 10 200
CL = 50pF
Doc. No. 25088-00 1/01
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CAT25C128/256
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C128/256 to interface directly with many of today's popular microcontrollers. The CAT25C128/256 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed.
CS Chip Select CS: CS is the Chip select pin. CS low enables the CAT25C128/ 256 and CS high disables the CAT25C128/256. CS high takes the SO output pin to high impedance and forces the device into a Standby Mode (unless an internal write operation is underway) The CAT25C128/256 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP Write Protect WP: WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. HOLD Hold HOLD: HOLD is the HOLD pin. The HOLD pin is used to pause transmission to the CAT25C128/256 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence.
PIN DESCRIPTION
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C128/256. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C128/256. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 25C128/256. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK.
INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
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Doc. No. 25088-00 1/01
CAT25C128/256
STATUS REGISTER
The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C128/ 256 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BPO and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed STATUS REGISTER 7 WPEN 6 X 5 X 4 X
to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero.
3 BP1
2 BP0
1 WEL
0 RDY
BLOCK PROTECTION BITS Status Register Bits BP1 BPO Array Address Protected 25C128 0 0 1 1 0 1 0 1 None 3000-3FFF 2000-3FFF 0000-3FFF 25C256 None 6000-7FFF 4000-7FFF 0000-7FFF No Protection Quarter Array Protection Half Array Protection Full Array Protection Protection
WRITE PROTECT ENABLE OPERATION Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
WPEN 0 0 1 1 X X
WP X X Low Low High High
WEL 0 1 0 1 0 1
Doc. No. 25088-00 1/01
6
CAT25C128/256
After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address (7FFFh for 25C256 and 3FFFh for 25C128) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle.Read sequence is illustrated in figure 4. Reading status register is illustrated in figure 5.
DEVICE OPERATION
Write Enable and Disable The CAT25C128/256 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C128/256, followed by the 16-bit address (the Most Significant Bit is don't care for 25C256 and the two most significant bits are don't care for the 25C128). Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
0
1
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) -- -- -- --
Figure 3. WRDI Instruction Timing
CS
SK
SI
0
0
0
0
0
1
0
0
SO Note: Dashed Line= mode (1, 1) -- -- -- --
HIGH IMPEDANCE
7
Doc. No. 25088-00 1/01
CAT25C128/256
WRITE Sequence The CAT25C128/256 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C128/256. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C128/256. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Figure 4. Read Instruction Timing
CS 0 SK
OPCODE
Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the most significant bit is don't care for 25C256 and the two most significant bits are don't care for the 25C128), and then the data to be written. Programming will start after the CS is brought high. The low to high transition of the CS pin must occur during the SCK low time, immediately after clocking the least significant bit of the data. Figure 6 illustrates byte write sequence.
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
SI
0
0
0
0
0
0
1
1
BYTE ADDRESS*
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) -- -- -- --
Figure 5. RDSR Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI
0
0
0
0
0
1
0
1
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
Note: Dashed Line= mode (1, 1) -- -- -- --
Doc. No. 25088-00 1/01
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CAT25C128/256
address will remain constant.The only restriction is that the 64 bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. The CAT25C128/256 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register.
During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction Page Write The CAT25C128/256 features page write capability. After the initial byte the host may continue to write up to 64 bytes of data to the CAT25C128/256. After each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of Figure 6. Write Instruction Timing
CS 0 SK
OPCODE
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
DATA IN
SI
0
0
0
0
0
0
1
0
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) -- -- -- --
Figure 7. WRSR Timing
CS 0 SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
SI
0
0
0
0
0
0
0
1
7
MSB
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) -- -- -- --
Figure 8. Page Write Instruction Timing
CS
0 SK
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
OPCODE
DATA IN
SI
0
0
0
0
0
0
1
0
ADDRESS
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte N 0 7..1
SO
Note: Dashed Line= mode (1, 1) -- -- -- --
HIGH IMPEDANCE
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Doc. No. 25088-00 1/01
CAT25C128/256
DESIGN CONSIDERATIONS The CAT25C128/256 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C128/256 goes into a write disable mode. CS must be set high after the proper number of clock cycles Figure 9. HOLD Timing
CS tCD SCK tHD HOLD tHZ SO
HIGH IMPEDANCE
to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again.
tCD
tHD
tLZ
Note: Dashed Line= mode (1, 1) -- -- -- --
Figure 10. WP Timing
tWPS
tWPH
CS
tCSH
SCK
WP
WP
Note: Dashed Line= mode (1, 1) -- -- -- --
Doc. No. 25088-00 1/01
10
CAT25C128/256
ORDERING INFORMATION
Prefix CAT Device # 25C256 Product Number 25C128: 128K 25C256: 256K K Suffix I Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40 to +105C)* - 1.8 TE13
Optional Company ID
Tape & Reel TE13: 2000/Reel
Package P = 8-Pin PDIP S = 8-Pin SOIC (JEDEC) S16 = 16-Pin SOIC (JEDEC) K = 8-Pin SOIC (EIAJ) U14 = 14-Pin TSSOP U20 = 20-Pin TSSOP * -40C to +125C is available upon request
Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V)
Notes: (1) The device used in the above example is a 25C256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel)
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Doc. No. 25088-00 1/01

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